1. Field of the Invention
The present invention relates to a logical circuit which is carried on a semiconductor device and outputs the output signals in which the period of the logic level (H) does not overlap even when the logical circuit receives the input signals in which the period of the logic level (H) partially overlaps.
2. Description of the Related Art
As a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap, the EX-OR (exclusive-or) circuit is well known.
In a case of the EX-OR circuit, the output signal will be influenced by one of the input signals at the time of rising of the other of the input signals.
This is a significant problem for a certain circuit, such as a DLL (delay-locked loop) circuit in which the timing of rising of the signals is important. In a semiconductor device carrying the circuit which operates at a high speed synchronized with the clock signal, a variation of phase in the clock signal may arise due to signal transmission delay or the like.
When a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap is added to the semiconductor device and used together in order to reduce such phase variation of the clock signal as much as possible, consideration must be taken on the conformity of the logical circuit with the circuit in which the timing of rising of the signals is important.
For this reason, it is demanded to provide a logical circuit which outputs the signals in which the period of the logic level (H) does not overlap and can be used suitably with the circuit, such as the DLL circuit in which the timing of rising of the signals is important, in such a manner that rising of the signal is not affected but falling of the signal is affected.
FIG. 1A shows an example of the conventional logical circuit. FIG. 1B shows the signal waveform of the input signals A and B to the logical circuit of FIG. 1A, and the output signals C and D from the logical circuit.
The logical circuit of FIG. 1A is a general EX-OR circuit that outputs the signals in which the period of the logic level (H) does not overlap.
The EX-OR circuit comprises the inverter 1, the inverter 2, the inverter 3, the inverter 4, the NOR gate 5, and the NOR gate 6.
In the EX-OR circuit of FIG. 1A, the input signal A is inputted to the inverter 1, and the input signal B is inputted to the inverter 2. The output of the inverter 1 is inputted to one input of the NOR gate 5 while it is inputted to the inverter 3. The output of the inverter 2 is inputted to one input of the NOR gate 6 while it is inputted to the inverter 4.
The output of the inverter 3 is inputted to the other input of the NOR gate 6. The output of the inverter 4 is inputted to the other input of the NOR gate 5. The NOR gate 5 receives the outputs from the inverter 1 and the inverter 4 and outputs the output signal C, and the NOR gate 6 receives the outputs from the inverter 2 and the inverter 3 and outputs the output signal D.
Consideration will now be taken to the case where the phase of the input signal A and the input signal B is shifted somewhat with reference to FIG. 1B.
The input signal A and the input signal B are, for example, the two clock signals which have different phases.
To these input clock signals, the variation in the phase may arise due to transmission delay of the clock signals in the semiconductor device carrying the circuit which operates at the high speed synchronized with the clock signals.
As shown in FIG. 1B, when the input signal B is at the logic level (L) at the instant the input signal A has changed from the logic level (L) to the logic level (H) (the time of rising), the phase of the input signal A transfers to the phase the output signal C as it is.
However, when the input signal B is at the logic level (H) at the time of rising of the input signal A, the output signal C still remains at the logic level (L).
When the input signal B changes from the logic level (H) to the logic level (L), the phase of the input signal A transfers to the phase of the output signal C for the first time.
That is, the time of rising of the input signal A will be delayed until the phase of the input signal B changes to the logic level (L), and then the output signal C will be outputted.
In other words, the EX-OR circuit of FIG. 1A operates such that the portion in which the logic level (H) of the input signal A overlaps with the input signal B is deleted from the portion in which the phase is changed from the logic level (L) to the logic level (H), and the overlapping of the logic level (H) of the output signal is eliminated.
However, when the method of the EX-OR circuit is applied to the circuit like the DLL circuit in which the timing of rising is important, the delay of the timing of rising is affected by the counterpart signal, and excessive delay time (loss) may arise, which will become the factor which worsens the underflow of the DLL circuit (which indicates the circuit performance with the delay minimum value).
Moreover, FIG. 2 is a diagram for explaining operation of the conventional logical circuit of FIG. 1A when the phase shift of the input signals occurs at intervals of the period of some cycles.
As shown in FIG. 2, when a phase shift of the input signal B to the input signal A occurs at intervals of some cycles, rather than the case where the phase shift occurs for every cycle, the conventional logical circuit may also cause the deviation of the phase of the input signal A.